SCSP

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The SCSP (Saturn Custom Sound Processor) is a rather nice sound processor by Yamaha (it is also used in a number of SEGA arcade hardware such as the ST-V, Model 2, and Model 3). It has 32 FM/PCM channels and a sample rate of 44.1khz; a built-in DSP that can apply all sorts of effects up to 16 inputs; a built-in MIDI controller that allows one to easily hook up a MIDI-device too (although it's unfortunately not used on a Saturn), and a number of other features that I'll go into sometime.

Common Control Registers

These are the main registers for controlling the SCSP. Everything from adjusting the memory mapping to interrupts to dma's are controlled by these registers. These registers start at 0x25B00400 when accessed from the SH2, or 0x100400 when accessed from the 68K. They continue on until 0x25B00430(or 0x100430). We'll use 68k addresses for the sake of simplicity.

Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 What's there
0x100400 - - - - - - 1 2 3 3 3 3 4 4 4 4 1:MEM4MB(Memory size)
2:DAC18B(DAC output size)
3:VER(SCSP version number)
4:MVOL(Master volume)
0x100402 - - - - - - - 1 1 2 2 2 2 2 2 2 1:RBL(Ring buffer length)
2:RBP(Ring buffer pointer)
0x100404 - - - 1 2 3 4 5 6 6 6 6 6 6 6 6 1:MOFULL(MIDI output full)
2:MOEMP(MIDI output empty)
3:MIOVF(MIDI input overflow)
4:MIFULL(MIDI input full)
5:MIEMP(MIDI input empty)
6:MIBUF(MIDI input buffer)
0x100406 - - - - - - - - 1 1 1 1 1 1 1 1 1:MOBUF(MIDI output buffer)
0x100408 1 1 1 1 1 2 2 2 2 - - - - - - - 1:MSLC(Monitor slot)
2:CA(Call Address)
0x100412 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1:DMEAL(DMA transfer start memory address low)
0x100414 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 - 1:DMEAH(DMA transfer start memory address high)
2:DRGA(DMA transfer start register address)
0x100416 - 1 2 3 4 4 4 4 4 4 4 4 4 4 4 - 1:DGATE(DMA transfer gate 0 clear)
2:DDIR(DMA transfer direction)
3:DEXE(DMA execute)
4:DTLG(DMA transfer count)
0x100418 - - - - - 1 1 1 2 2 2 2 2 2 2 2 1:TACTL(Timer A control)
2:TIMA(Timer A counter)
0x10041A - - - - - 1 1 1 2 2 2 2 2 2 2 2 1:TBCTL(Timer B control)
2:TIMB(Timer B counter)
0x10041C - - - - - 1 1 1 2 2 2 2 2 2 2 2 1:TCCTL(Timer C control)
2:TIMC(Timer C counter)
0x10041E - - - - - 1 1 1 1 1 1 1 1 1 1 1 1:SCIEB(Sound CPU interrupt enable)
0x100420 - - - - - 1 1 1 1 1 1 1 1 1 1 1 1:SCIPD(Sound CPU interrupt pending)
0x100422 - - - - - 1 1 1 1 1 1 1 1 1 1 1 1:SCIRE(Sound CPU interrupt reset)
0x100424 - - - - - - - - 1 1 1 1 1 1 1 1 1:SCILV0(Sound CPU interrupt level bit 0)
0x100426 - - - - - - - - 1 1 1 1 1 1 1 1 1:SCILV1(Sound CPU interrupt level bit 1)
0x100428 - - - - - - - - 1 1 1 1 1 1 1 1 1:SCILV2(Sound CPU interrupt level bit 2)
0x10042A - - - - - 1 1 1 1 1 1 1 1 1 1 1 1:MCIEB(Main CPU interrupt enable)
0x10042C - - - - - 1 1 1 1 1 1 1 1 1 1 1 1:MCIPD(Main CPU interrupt pending)
0x10042E - - - - - 1 1 1 1 1 1 1 1 1 1 1 1:MCIRE(Main CPU interrupt reset)


Timer Registers

Basically these are free-running timers that count from 0x00-0xFF. Once 0xFF is reached, the SCSP sets the corresponding bit in SCIPD and MCIPD. And if the same corresponding bits are set in SCIEB and MCIEB, it triggers an interrupt as well. In order to clear SCIPD/MCIPD, write the same corresponding bit to SCIRE/MCIRE. That will enable you to trigger an interrupt again.

You can adjust the timer speed by setting the TIMX portion of the Timer register. Here's a chart that explains the timing:

TXCTL Value Timing(time it takes to increment counter by 1)
0 1/44100 of a second
1 2/44100 of a second
2 4/44100 of a second
3 8/44100 of a second
4 16/44100 of a second
5 32/44100 of a second
6 64/44100 of a second
7 128/44100 of a second

-Remember-, these are free-running timers. As soon as 0xFF is reached, the SCSP will immediately start from 0 again and start counting. If you need more consistent counting, remember to reset the counter portion of the Timer to 0 before you reset the interrupt using SCIRE/MCIRE.

Other notes: When you set any of the bits in MCIEB/SCIEB to 1, if any of their corresponding bits in MCIPD/SCIPD are set, an interrupt will immediately be triggered. So make sure you clear them with MCIRE/SCIRE -first- before you enable them.

Individual slot registers

Each FM/PCM channel has a set of registers called slot registers. These control all the important things surrounding the individual channels such as key on/off, data type, start address, looping, pitch, special effects, etc. These registers start at 0x25B00000 when accessed from the SH2, or 0x100000 when accessed from the 68K. Each set is 32 bytes in size and continues on till 0x25B00400(or 0x100400).

Slot register offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 What's there
0x00 - - - 1 2 3 3 4 4 5 5 6 7 7 7 7 1:KYONEX(key on execute)
2:KYONB(key on bit)
3:SBCTL(source bit control)
4:SSCTL(sound source control)
5:LPCTL(loop control)
6:PCM8B(pcm 8-bit)
7:SA(start address)
0x02 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1:SA(start address)
0x04 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1:LSA(loop start address as number of samples from start address)
0x06 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1:LEA(loop end address as number of samples from start address)
0x08 1 1 1 1 1 2 2 2 2 2 3 4 4 4 4 4 1:D2R(decay 2 rate)
2:D1R(decay 1 rate)
3:EGHOLD(eg hold mode)
4:AR(attack rate)
0x0A - 1 2 2 2 2 3 3 3 3 3 4 4 4 4 4 1:LPSLNK(loop start link)
2:KRS(key rate scaling)
3:DL(decay level)
4:RR(release rate)
0x0C - - - - - - 1 2 3 3 3 3 3 3 3 3 1:STWINH(stack write inhibit)
2:SDIR(sound direct)
3:TL(total level)
0x0E 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1:MDL(modulation level)
2:MDXSL(modulation input x)
3:MDYSL(modulation input y)
0x10 - 1 1 1 1 - 2 2 2 2 2 2 2 2 2 2 1:OCT(octave)
2:FNS(frequency number switch)
0x12 1 2 2 2 2 2 3 3 4 4 4 5 5 6 6 6 1:LFORE(LFO reset)
2:LFOF(LFO frequency)
3:PLFOWS(pitch LFO wave select)
4:PLFOS(pitch LFO displacement)
5:ALFOWS(amplitude LFO wave select)
6:ALFOS(amplitude LFO displacement)
0x14 - - - - - - - - - 1 1 1 1 2 2 2 1:ISEL(input select)
2:OMXL(input mix level)
0x16 1 1 1 2 2 2 2 2 3 3 3 4 4 4 4 4 1:DISDL(direct/dry level)
2:DIPAN(direct/dry pan)
3:EFSDL(effect/wet level)
4:EFPAN(effect/wet pan)

KYONEX/KYONB

The KYONEX register executes a key on/key off to all channels. Which it does depends on the value of the KYONB register. In more simple terms, in order to to use it, you first write to the channel's KYONB bit you want to change key on/off status(1 for key on, 0 for key off) while leaving KYONEX as 0. Then to apply the changes, write to any channel's KYONEX bit with 1 set to execute the changes to all channels.

SBCTL register notes

Normally the SCSP works with signed 8-bit/16-bit samples by default. What the SBCTL alows you to do is xor the sign bit or the other bits depending on the setting. So you can use unsigned samples or other wackiness. Refer to the following chart:

SBCTL bit What it does when set
0 XOR other bits other than sign bit
1 XOR sign bit

SSCTL register notes

The sound source control register tells the SCSP what kind of source you want input into the slot. Normally you'd use the sound ram, but you can also select internally generated noise or blank audio. Refer to the following chart:

SSCTL Source
0 Sound Ram
1 Noise(internally generated)
2 Blank audio(internally generated)
3 Unknown

TL register notes

The total level register basically acts as a kind of pre-mixing volume adjustment. If this is set to 0, no volume adjustment is done. Any other value lowers the volume. You can adjust it in 0.3762 dB increments(so basically the max attenuation is approximately -95.9 dB). This is handy if you're using a bunch of slots and you're worried about clipping issues.

OCT register notes

The OCT register controls the octave of the sound output on each channel. The default value of 0x0 means that there is no change to the pitch of the sound as its played. Refer to the following chart:

OCT Frequency Adjustment
0x8 Divide by 256
0x9 Divide by 128
0xA Divide by 64
0xB Divide by 32
0xC Divide by 16
0xD Divide by 8
0xE Divide by 4
0xF Divide by 2
0x0 No change
0x1 Multiply by 2
0x2 Multiply by 4
0x3 Multiply by 8
0x4 Multiply by 16
0x5 Multiply by 32
0x6 Multiply by 64
0x7 Multiply by 128